1. Field of the Invention
The present invention relates generally to a multi-chip semiconductor memory device having a plurality of memory chips, and more particularly, to a multi-chip semiconductor memory device having a plurality of memory chips, each including internal power supply voltage generation circuits which independently convert an external power supply voltage into an internal power supply voltage.
2. Description of the Related Art
A memory chip includes an internal power supply voltage generation circuit which may generate a low-level internal power supply voltage by converting an external power supply voltage into the internal power supply voltage. Power consumption of the memory chip may be decreased by using such an internal power supply voltage generation circuit. Furthermore, even though the external power supply voltage may change, the internal power supply voltage may be kept relatively uniform, so that the memory chip can maintain a uniform operation voltage. Generally, a single memory chip may include a standby internal power supply voltage generation circuit and an active internal power supply voltage circuit. The standby internal power supply generation circuit may have a small capacity and may be driven by an external power supply voltage. On the other hand, the active internal power supply voltage generation circuit may have a large capacity and may be enabled at the time of activation.
New electronic devices are becoming smaller and lighter due to developments in semiconductor fabrication technology and user demand. These developments have lead to the manufacturing of a multi-chip semiconductor memory device in which a plurality of memory chips are mounted in a single package.
FIG. 1 is a diagram illustrating a conventional multi-chip semiconductor memory device. As illustrated in FIG. 1, a plurality of memory chips 10<1:n> are mounted in the multi-chip semiconductor memory device. Furthermore, the plurality of memory chips 10 share a chip enable signal /CE. Each of the plurality of memory chips includes an active internal power supply voltage generation circuit 11 and a standby internal power supply voltage generation circuit 13. The busy indication signal generation circuit 15 of each memory chip 10 generates a busy indication signal RNB, which is shared by the memory chips 10. Furthermore, the control signal generation circuit 17 of each memory chip 10 generates an operation control signal which controls its busy indication generation circuit 15 in response to an external command COMM and chip selection information CSIF.
While the conventional multi-chip semiconductor memory device includes a plurality of memory chips, it has several limitations. For example, as illustrated in FIG. 2, the chip enable signal /CE controls the enabling of all the active internal power supply voltage generation circuits 11. Therefore, although only one memory chip 10 may be in an active interval, the active internal power supply voltage generation circuits 11 of the inactive memory chips 10 are also enabled. The enabling of all the active internal power supply generation circuits 11 despite not all the memory chips being in an active interval may cause unnecessary power consumption in the active internal power supply voltage generation circuits.
The present disclosure is directed to overcoming one or more of the problems associated with the conventional multi-chip semiconductor memory devices.